1. Field of Invention
The present invention relates to the etching of dielectric materials. More particularly, the present invention is related to the etching of dielectric materials used as interconnect dielectrics in semiconductor fabrication.
2. Description of Related Art
In semiconductor integrated circuit (IC) fabrication, devices such as component transistors are formed on a semiconductor wafer substrate that is typically made of silicon. During the fabrication process, various materials are deposited on the different layers in order to build a desired IC. Typically, conductive layers may include patterned metallization lines, polysilicon transistor gates and the like, are insulated from one another with dielectric materials. The dielectric materials have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitances.
In general, the coupling capacitance in an integrated circuit is directly proportion to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
As a result a substantial degree of research is being conducted into the use of low-k dielectric materials. Low-k dielectrics can be categorized as follows: doped oxide, organic, highly fluorinated, and porous materials. Low-k materials can be deposited either by spin-on or CVD methods. Porous materials typically use spin-on methods, with controlled evaporation of the solvent providing the desired pore structure. A table of typical low-k dielectrics is provided below.
Illustrative Classification of Low-k MaterialsFilm TypesSub-TypeExamplesk rangeDoped OxideF-dopedFSG3.5H-dopedHSQ2.7-3.5C (and H) dopedOSG, MSQ,2.6-2.8CVD low-kOrganicBCB, SiLK, FLARE,2.6-2.8PAE-2Highly FluorinatedParylene AF4, a-CF,2.0-2.5PTFEPorousAerogels, Xerogels,<2.2Nanogels
One of the well-known implementation strategies for incorporating low-k materials into IC fabrication includes the use of a copper dual damascene process. A dual damascene structure employs an etching process that creates trenches for lines and holes for vias which are then simultaneously metallized to form the interconnect wiring. The two well known dual damascene schemes are referred to as a via first sequence and a trench first sequence.
One well known illustrative via first sequence requires that a via is masked and a trench dielectric, a via dieletric and an intermediate etch-stop layer are etched and the etching stops at a barrier layer such as silicon nitride. The wafer is then re-patterned for the subsequent trench and this pattern etched, stopping on the intermediate etch-stop layer. In some cases, the via is covered by a photoresists or organic ARC plug that protects the via and the underlying barrier nitride during the trench etch process. The trench first sequence is similar to the via first sequence only the trench is etch before the via is etched.
One of the limitations of the prior art dielectric structures is that these structures contain an intermediate etch stop layer. The intermediate etch stop layer creates two substantial problems. The first problem is the intermediate etch stop layer generally has a high dielectric constant and contributes to capacitive coupling within the structure. Additionally, the intermediate etch stop layer adds another process layer to formation of dielectric wafer.
Therefore, it would be beneficial to develop a method for etching low-k dielectric materials without the use of an intermediate etch-stop layer.
It would also be beneficial to provide a method that simplifies the manufacturing of low-k dielectric wafers by not requiring an intermediate etch-stop layer.
However, the removal of the intermediate etch-stop layer in a low-k dielectric creates additional challenges that the prior art has not overcome. These challenges include controlling critical dimensions (CD) by controlling via depth and trench depth and creating structures that are smooth and flat.
Therefore it would be beneficial to provide a method for processing low-k dielectric materials that is capable of maintaining CD control.
It would also be beneficial to provide a method for processing low-k dielectric materials to achieve controlled trench and via depth.